1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly, to a semiconductor memory device with plural power supply voltages at respective different voltage levels, capable of reducing a leakage current flowing into a substrate.
2. Description of the Background Art
Attention has been focused on DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory) and so on as a memory capable of inputting/outputting data at high speed.
Referring to FIG. 33, a prior art semiconductor memory device 1000 includes: memory cells 1001 and 1002; a sense amplifier 1010; a gate circuit 1020; peripheral circuit 1030; and a bit line driver 1070. Note that FIG. 33 shows only a part of semiconductor memory device 1000 since the figure is to describe fundamental operation of semiconductor memory device 1000.
Memory cell 1001 is connected to a bit line BL and a word line W1. Memory cell 1002 is connected to a bit line /BL and a word line W2. When word line W1 is activated, memory cell 1001 outputs data onto bit line BL or data is inputted to memory cell 1001 from bit line BL. When word line W2 is activated, memory cell 1002 outputs data onto bit line /BL or data is inputted to memory cell 1002 from bit line /BL.
Sense amplifier 1010 includes P channel MOS transistors 1011 to 1013; and N channel MOS transistors 1014 to 1016. P channel NOS transistor 1011 is connected between a power supply node 1017 and a node 1031 and receives a sense amplifier activation signal /SE at the gate terminal thereof. P channel MOS transistor 1012 and N channel MOS transistor 1014 are connected in series between nodes 1031 and 1032. P channel MOS transistor 1013 and N channel MOS transistor 1015 are connected in series between nodes 1031 and 1032. P channel MOS transistor 1012 and N channel MOS transistor 1014 in series connection are connected in parallel to P channel MOS transistor 1013 and N channel MOS transistor 1015 in series connection. N channel MOS transistor 1016 is connected between node 1032 and a ground node 1018 and receives a sense amplifier activation signal SE at the gate terminal thereof.
A node 1033 is connected to bit line BL. A node 1034 is connected to bit line /BL. P channel MOS transistor 1012 and N channel MOS transistor 1014 receive a voltage on bit line BL at the gate terminals thereof. P channel MOS transistor 1013 and N channel MOS transistor 1015 receive a voltage on bit line /BL at the gate terminals thereof. An array power supply voltage VccA is supplied onto power supply node 1017 and ground voltage is supplied onto ground node 1018.
When word line W1 is activated and data [1] is read out from memory cell 1001, the voltage on bit line BL comes to be voltage VccA/2+xcex1 slightly higher than a precharge voltage VccA/2 and bit line /BL assumes a precharge voltage VccA/2. In such a state, sense amplifier activation signal SE at H (logical high) level is inputted to sense amplifier 1010. Thereby, sense amplifier 1010 is activated. Voltage VccA/2+xcex1 is transmitted along bit line BL and applied onto the gate terminals of P channel MOS transistor 1012 and N channel MOS transistor 1014. Then, P channel MOS transistor 1012 is turned off, while N channel MOS transistor 1014 is turned on, with the result that a voltage on node 1034 is lowered to ground voltage (0 V) and in turn, a voltage on bit line /BL comes to 0 V.
Since a voltage on bit line /BL is applied to the gate terminals of P channel MOS transistor 1013 and N channel MOS transistor 1015, P channel MOS transistor 1013 is turned on, while N channel MOS transistor 1015 is turned off to cause a voltage on node 1033 to be array power supply voltage VccA. Then, a voltage on bit line BL becomes array power supply voltage VccA. In such operation, voltages on bit lines BL and /BL showing data [1] read out from memory cell 1001 are amplified from (VccA/2+xcex1, VccA/2) to (VccA, 0), respectively.
When data [0] is read out from memory cell 1001, a voltage on bit line BL becomes a voltage VccA/2xe2x88x92xcex1 slightly lower than precharge voltage VccA/2, and a voltage on bit line /BL becomes precharge voltage VccA/2. Voltage VccA/2 is transmitted along bit line /BL and applied onto the gate terminals of P channel MOS transistor 1013 and N channel MOS transistor 1015 of sense amplifier 1010. Then, P channel MOS transistor 1013 is turned off, while N channel MOS transistor 1015 is turned on to cause a voltage on node 1033 to be ground voltage (0V). Thus, a voltage on bit line BL becomes 0 V.
Since a voltage on bit line BL is applied onto the gate terminals of P channel MOS transistor 1012 and N channel MOS transistor 1014, P channel MOS transistor 1012 is turned on, while N channel MOS transistor 1014 is turned off to cause a voltage on node 1034 to be array power supply voltage VccA. Then, a voltage on bit line /BL becomes array power supply voltage VccA. In such operation, voltages on bit lines BL and /BL showing data [0] read out from memory cell 1001 are amplified from (VccA/2xe2x88x92xcex1, VccA/2) to (0, VccA), respectively.
When data is read out from memory cell 1002, as well, sense amplifier 1010 amplifies voltages on bit lines BL and /BL performing the above operation.
When data is written onto memory cells 1001 and 1002, sense amplifier 1010 transfers voltages transmitted from a global data line pair GIO and /GIO as VccA and 0 (or 0 and VccA) onto bit line pair BL and /BL, respectively.
Therefore, sense amplifier 1010 amplifies data read out from memory cells 1001 and 1002 using a cross-coupled latch, or alternatively transfers data written from outside semiconductor memory device 1000 onto bit lines BL and /BL using the cross-coupled latch.
Gate circuit 1020 includes N channel MOS transistors 1021 and 1022. N channel MOS transistor 1021 is connected to bit line BL at the drain terminal thereof and to global data line GIO at the source terminal, and receives a column select signal VACSL at the gate terminal thereof. N channel MOS transistor 1022 is connected to bit line /BL at the drain terminal thereof and to global data line /GIO at the source terminal, and receives column select signal VACSL at the gate terminal thereof. Therefore, N channel MOS transistor 1021 is turned on when receiving column select signal VACSL at H level at the gate terminal thereof to connect global data line GIO to bit line BL. N channel MOS transistor 1022 is turned on when receiving column select signal VACSL at the gate terminal thereof to connect global data line /GIO to bit line /BL.
Peripheral circuit 1030 includes: a GIO line write driver 1040; a read amplifier 1050; and a GIO line equalize circuit 1060. GIO line write driver 1040 includes: inverters 1041 and 1044 to 1047; NAND gates 1042 and 1043; P channel MOS transistors 1048 and 1051; and N channel MOS transistors 1049 and 1052. Inverter 1041 inverts a signal inputted at terminal 1028 to output the inverted input to one terminal of NAND gate 1043. NAND gate 1042 receives a signal inputted at terminals 1028 and 1029 to invert a logical product of the received two signals and output the inverted logical product as a signal. NAND gate 1043 receives an output signal of inverter 1041 and a signal inputted at terminal 1029 to invert a logical product of the received two signals and output the inverted logical product as a signal. Inverter 1044 inverts an output signal of NAND gate 1042. Inverter 1045 inverts an output signal of NAND gate 1043. Inverter 1046 inverts an output signal of inverter 1044. Inverter 1047 inverts an output signal of inverter 1045.
P channel MOS transistor 1048 and N channel MOS transistor 1049 are connected in series between a power supply node 1053 and a ground node 1054. P channel MOS transistor 1048 receives an output signal of inverter 1046 at the gate terminal thereof. N channel MOS transistor 1049 receives an output signal of inverter 1045 at the gate terminal thereof.
P channel MOS transistor 1051 and N channel MOS transistor 1052 are connected in series between power supply node 1053 and ground node 1054. P channel MOS transistor 1051 receives an output signal of inverter 1047 at the gate terminal thereof. N channel MOS transistor 1052 receives an output signal of inverter 1044 at the gate terminal thereof.
Global data line GIO is connected to a node 1055 between P channel MOS transistor 1048 and N channel MOS transistor 1049. Furthermore, global data line /GIO is connected to a node 1056 between P channel MOS transistor 1051 and N channel MOS transistor 1052. Power supply voltage Vcc lower than array power supply voltage VccA is supplied to power supply node 1053 and ground voltage (0 V) is supplied to ground node 1054.
When data is written, a signal WM of H level is inputted at terminal 1029 and a signal WD of H level or L (logical low) level corresponding to data [1] or [0] is inputted at terminal 1028. When data [1] is written, signal WD of H level is inputted at terminal 1028 and signal WD of H level is inputted at terminal 1029. Subsequently, inverter 1041 outputs a signal of L level, NAND gate 1043 outputs a signal of H level and inverter 1045 outputs a signal of L level. Then, inverter 1047 outputs a signal of H level.
On the other hand, NAND gate 1042 outputs a signal of L level and inverter 1044 outputs a signal of H level. Then, inverter 1046 outputs a signal of L level.
In such a situation, P channel MOS transistor 1048 and N channel MOS transistor 1052 are turned on, while N channel MOS transistor 1049 and P channel MOS transistor 1051 are turned off. Then, GIO line driver 1040 supplies power supply voltage Vcc onto global data line GIO and ground voltage onto global data line /GIO.
When data [0] is written, signal WD of L level is inputted at terminal 1028 and signal WM of H level is inputted at terminal 1029. Then, inverter 1041 outputs a signal of H level, NAND gate 1043 outputs a signal of L level, and inverter 1045 outputs a signal of H level. Receiving the signal of H level from inverter 1045, inverter 1047 outputs a signal of L level.
On the other hand, NAND gate 1042 outputs a signal of H level and inverter 1044 outputs a signal of L level. Receiving the signal of L level from inverter 1044, inverter 1046 outputs a signal of H level.
In such a situation, N channel MOS transistor 1049 and P channel MOS transistor 1051 are turned on, while P channel MOS transistor 1048 and N channel MOS transistor 1052 are turned off. Then, GIO line driver 1040 supplies ground voltage onto global data line GIO and power supply voltage Vcc onto global data line /GIO.
Note that when signal WM of L level is inputted at terminal 1029, NAND gates 1042 and 1043 output a signal of H level regardless of a logical level of a signal inputted at terminal 1028 and therefore, inverters 1044 and 1045 output signals of L level. With the signals of L level from inverters 1044 and 1045, inverters 1046 and 1047 output signals of H level. In such a situation, P channel MOS transistors 1048 and 1051 and N channel MOS transistors 1049 and 1052 are all turned off to put global data line pair GIO ad /GIO into floating state, where no data write is performed.
In such a manner, GIO line write driver 1040 supplies voltages (Vcc, 0) or (0, Vcc) to global data line pair GIO and /GIO, respectively, in response to data inputted at terminal 1028.
Read amplifier 1050 receives data read out from memory cell 1001 or 1002 through global data line GIO and /GIO to amplify the received data and output the read data to an input/output terminal.
GIO line equalize circuit 1060 is constructed of a P channel MOS transistors 1061 to 1063. P channel MOS transistor 1061 is connected between global data lines GIO and /GIO. P channel MOS transistors 1062 and 1063 are connected in series between global data lines GIO and /GIO. Power supply voltage Vcc is supplied to a node 1064 from a power supply node 1065. P channel MOS transistors 1061 to 1063 receive a GIO line equalize signal GIOEQ at the gate terminals thereof.
When GIO line equalize signal GIOEQ of L level is inputted to GIO line equalize circuit 1060, P channel MOS transistors 1061 to 1063 are turned on and GIO line equalize circuit 1060 supplies power supply voltage Vcc onto both of global data line pair GIO and /GIO from node 1064. In this situation, since P channel MOS transistor 1061 is in on state, potentials on global data lines GIO and /GIO are equal to each other, thus equalizing global data line pair GIO and /GIO.
Bit line driver 1070 includes: a P channel MOS transistor 1071 and an N channel MOS transistor 1072. P channel MOS transistor 1071 and N channel MOS transistor 1072 are connected in series between a power supply node 1073 and a ground node 1074. A power supply voltage VccP is supplied to power supply node 1073. Bit line driver 1070 is included in a column decoder and inputted with a signal of H level or L level in response to a decoded column address.
When bit line pair BL and /BL corresponding to bit line driver 1070 is selected, P channel MOS transistor 1071 and N channel MOS transistor 1072 receives a signal of L level at the gate terminals thereof. As a result, P channel MOS transistor 1071 is turned on, while N channel MOS transistor 1072 is turned off, and bit line driver 1070 outputs column select signal VACSL composed of power supply voltage VccP to gate circuit 1020.
When bit line pair BL and /BL corresponding to bit line driver 1070 is not selected, P channel MOS transistor 1071 and N channel MOS transistor 1072 receive a signal of H level. As a result, P channel MOS transistor 1071 is turned off, while N channel MOS transistor 1072 is turned on, and bit line driver 1070 outputs column select signal VACSL composed of ground voltage to gate circuit 1020.
When data is inputted to or outputted from memory cell 1001 (or 1002), GIO line equalize circuit 1060 receives GIO line equalize signal GIOEQ of L level to supply power supply voltage Vcc to both of global data line GIO and /GIO and equalize global data line GIO and /GIO, as described above. Then, GIO line equalize signal GIOEQ of H level is inputted to GIO line equalize circuit 1060 and P channel MOS transistors 1061 to 1063 are turned off, thereby completing equalization of global data line pair GIO and /GIO.
After the equalization of global data line pair GIO and /GIO, bit line driver 1070 outputs column select signal VACSL composed of power supply voltage VccP to gate circuit 1020 according to the way described above. Thereby, N channel MOS transistors 1021 and 1022 are turned on and gate circuit 1020 connects global data line pair GIO and /GIO to bit line pair BL and /BL, respectively.
Thereafter, when data is written onto memory cell 1001 (or 1002), GIO line write driver 1040 supplies voltages (Vcc and 0) or (0 and Vcc) to global data line pair GIO and /GIO as described above. Then, voltages on global data line pair GIO and /GIO are supplied onto bit line pair BL and /BL, respectively, through N channel MOS transistors 1021 and 1022.
With supply of the voltages onto bit line pair BL and /BL, sense amplifier 1010 transfers a voltage on a bit line supplied with power supply voltage Vcc of bit line pair BL and /BL as power supply voltage VccA to memory cell 1001 (or 1002).
When data is read out from memory cell 1001 (or 1002), sense amplifier 1010 sets voltages on bit line pair BL and /BL to (VccA and 0) or (0 and VccA), thus amplifying read data. When amplification of the read data in sense amplifier 1010 ends, bit line driver 1070 outputs column select signal VACSL composed of power supply voltage VccP to turn on N channel MOS transistors 1021 and 1022 of gate circuit 1020. By doing so, voltages on bit line pair BL and /BL are transmitted onto global data line pair GIO and /GIO, respectively, through N channel MOS transistors 1021 and 1022. In this case, global data line pair GIO and /GIO are equalized to power supply voltage Vcc before N channel MOS transistors 1021 and 1022 are turned on.
Accordingly, when data is inputted to or outputted from memory cell 1001 (or 1002), array power supply voltage VccA is applied onto the drain terminals (bit line pair BL and /BL sides) of N channel MOS transistors 1021 and 1022 in gate circuit 1020 and power supply voltage Vcc is supplied onto the source terminals (global data line pair GIO and /GIO sides) of N channel MOS transistors 1021 and 1022. Furthermore, power supply voltage VccP is applied onto the gate terminals of N channel MOS transistors 1021 and 1022.
Recently, however, in company with progress toward a high speed operation in a semiconductor memory device, MOS transistors constituting peripheral circuitry 1030 have been increasingly adopted a thin gate oxide film. With increase in adoption of a thin gate oxide film, power supply voltage Vcc of the peripheral circuitry has been in a trend toward a lower voltage, and set lower than array power supply voltage VccA of sense amplifier 1010. In such a situation, a problem arises since a leakage current flows into substrates of P channel MOS transistors constituting GIO line write driver 1040 and GIO line equalize circuit 1060 from bit line pair BL and /BL.
Moreover, in a case where plural MOS transistors with plural power supply voltages at respective different levels use an output node commonly among them, a problem arises since, when one of the power supply voltages varies largely, a forward leakage current of a PN junction flows to the substrate of a MOS transistor from an active region in which the drain of the MOS transistor is formed. That is, referring to FIG. 34, a P channel MOS transistor 1100 and an N channel MOS transistor 1101 are connected in series between power supply node 1102 and a ground node 1103. Furthermore, a P channel MOS transistor 1104 and an N channel MOS transistor 1105 are connected in series between a power supply node 1106 and a ground node 1107.
A power supply voltage Vcc1 is supplied onto power supply node 1102 and a ground voltage Vs1 is supplied onto a ground node 1103. A power supply voltage Vcc2 is supplied to power supply node 1106 and a ground voltage Vs2 is supplied onto a ground node 1107. P channel MOS transistor 1100 and N channel MOS transistor 1101 use an output node 1108 of P channel MOS transistor 1104 and N channel MOS transistor 1105 commonly therewith.
In such a configuration, when power supply voltage Vcc2 is higher than power supply voltage Vcc1, a bias in the forward direction is applied across the PN junction in the drain region of P channel MOS transistor 1100 and thereby, a leakage current flows into a substrate of P channel MOS transistor 1100. Furthermore, when ground voltage Vs2 is lower than ground voltage Vs1, a bias in the forward direction is applied across the PN junction in the drain region of P channel MOS transistor 1101 and thereby, a leakage current flows into a substrate of P channel MOS transistor 1101.
The leakage current shown in FIG. 34 occurs between a pair of P channel MOS transistor 1013 and N channel MOS transistor 1015 constituting sense amplifier 1010 and a pair of P channel MOS transistor 1048 and N channel MOS transistor 1049 constituting GIO line write driver 1040, shown in FIG. 33. Furthermore, the leakage current shown in FIG. 34 also occurs between a pair of P channel MOS transistor 1012 and N channel MOS transistor 1014 constituting sense amplifier 1010 and a pair of P channel MOS transistor 1051 and N channel MOS transistor 1052 constituting GIO line write driver 1040.
It is accordingly an object of the present invention to provide a semiconductor memory device driven by plural power supply voltages with respective different levels, capable of reducing a leakage current.
According to the present invention, a semiconductor memory device of the present invention comprises: plural memory cells; plural bit line pairs, provided correspondingly to the plural memory cells, and each for inputting or outputting data to or from a memory cell; plural sense amplifiers, provided correspondingly to the plural bit line pairs, and each supplying a first power supply voltage to one of a corresponding bit line pair when data is inputted to or outputted from a memory cell; plural global data line pairs provided correspondingly to the plural bit line pairs; a write/read circuit supplying a second power supply voltage lower than the first power supply voltage to one of a corresponding global data line pair when data is written onto a memory cell, and receiving the second power supply voltage from one of a corresponding global data line pair when data is read from a memory cell; a column decoder circuit outputting an activation signal for activating a bit line pair provided correspondingly to a memory cell onto or from which data is inputted or outputted among the plural bit line pairs when data is inputted to or outputted from the memory cell, and a deactivation signal for deactivating bit line pairs provided correspondingly to memory cells other than a memory cell onto or from which data is inputted or outputted; and plural gate circuits provided correspondingly to the plural bit line pairs and plural global data line pairs, wherein each of the plural gate circuits connects a corresponding bit line pair to a corresponding global data line pair when receiving the activation signal, while disconnecting a corresponding bit line pair from a corresponding global data line pair when receiving the deactivation signal, and a current flowing from the bit line pair toward the global data line pair through a gate circuit receiving the activation signal is smaller than a predetermined value.
Preferably, the activation signal is composed of a third power supply voltage and each of the plural gate circuits includes MOS transistors to be activated by the third power supply voltage.
Preferably, each of the plural gate circuits includes: a first MOS transistor connected to one of a global data line pair at a source terminal thereof and to one of a bit line pair at a drain terminal thereof, and receiving the third power supply voltage at a gate terminal thereof; and a second MOS transistor connected to the other of the global data line pair at a source terminal thereof and to the other of the bit line pair at a drain terminal thereof, and receiving the third power supply voltage at a gate terminal thereof, wherein when threshold voltages of the first and second MOS transistors are Vth, the second power supply voltage is Vcc and the third power supply voltage is VccP by definition, a relation VccPxe2x89xa6Vcc+Vth is satisfied.
Preferably, each of the plural gate circuits includes: a first MOS transistor of a first conductive type, connected to one of a global data line pair at a source terminal thereof and to one of a bit line pair at a drain terminal thereof, and receiving the third power supply voltage at a gate terminal thereof, and a second MOS transistor of the first conductive type, connected to the other of the global data line pair at a source terminal thereof, to the other of the bit line pair at a drain terminal thereof, and receiving the third power supply voltage at a gate terminal thereof and the write/read circuit includes: a third MOS transistor of a second conductive type, wherein when threshold voltages of the first and second MOS transistors are Vth, the second power supply voltage is Vcc, the third power supply voltage is VccP and a built-in potential of the third MOS transistor is Vb by definition, a relation VccPxe2x89xa6Vcc+Vth+Vb is satisfied.
Preferably, the activation signal is composed of the third power supply voltage generated in response to a voltage level of the second power supply voltage.
Preferably, the semiconductor memory device further comprises: a power supply voltage change-over circuit receiving a voltage level change-over signal for changing voltage levels of the third power supply voltage therebetween in response to a voltage level of the second power supply voltage to change over voltage levels of the third power supply voltage based on thus received voltage change-over signal and output the third power supply voltage with a changed voltage level to the column decoder circuit, wherein the column decoder circuit generates the activation signal composed of the third power supply voltage outputted by the power supply change-over circuit.
Preferably, each of the plural gate circuits includes: a first MOS transistor connected to one of a global data line pair at a source terminal thereof and to one of a bit line pair at a drain terminal thereof, and receiving the third power supply voltage at a gate terminal thereof; and a second MOS transistor connected to the other of the global data line pair at a source terminal thereof and to the other of the bit line pair at a drain terminal thereof, and receiving the third power supply voltage at a gate terminal thereof, wherein when threshold voltages of the first and second MOS transistors are Vth, the second power supply voltage is Vcc and the third power supply voltage is VccP by definition, a relation VccPxe2x89xa6Vcc+Vth is satisfied.
Preferably, each of the plural gate circuits includes: a first MOS transistor of a first conductive type, connected to one of a global data line pair at a source terminal thereof and to one of a bit line pair at a drain terminal thereof, and receiving the third power supply voltage at a gate terminal thereof; and a second MOS transistor of the first conductive type, connected to the other of the global data line pair at a source terminal thereof and to the other of the bit line pair at a drain terminal thereof, and receiving the third power supply voltage at a gate terminal thereof and the write/read circuit includes: a third MOS transistor of a second conductive type, wherein when threshold voltages of the first and second MOS transistors are Vth, the second power supply voltage is Vcc, the third power voltage is VccP and a built-in potential of the third MOS transistor is Vb by definition, a relation VccPxe2x89xa6Vcc+Vth+Vb is satisfied.
Preferably, the power supply voltage change-over circuit changes voltage over levels of the third power supply voltage based on a mode change-over signal.
Preferably, the power supply voltage change-over circuit changes voltage over levels of the third power supply voltage by means of changing wire bonding or changing masks.
Preferably, the power supply voltage change-over circuit receives the voltage level change-over signal from a decoding circuit changing modes.
Preferably, the semiconductor memory device further includes: a power supply voltage change-over circuit changing voltage levels of the third power supply voltage with reference to a reference voltage whose voltage level changes in response to a voltage level of the second power supply voltage.
Preferably, the power supply voltage change-over circuit includes: a reference voltage generation circuit generating plural reference voltages; a select circuit selecting a reference voltage in response to a voltage level of the second voltage among the plural reference voltages; and a step-down circuit reducing an external power supply voltage down to a selected reference voltage to generate the third power supply voltage.
Preferably, the power supply voltage change-over circuit includes: a reference voltage generation circuit generating a reference voltage with a different voltage level by changing a voltage division ratio for an external power supply voltage in response to a voltage level of the second power supply voltage; and a step-down circuit reducing the external power supply voltage down to the reference voltage received from the reference voltage generation circuit to generate the third power supply voltage.
Furthermore, according to the present invention, a semiconductor memory device of the present invention includes: plural power supply terminals for supplying plural power supply voltages with different voltage levels; plural ground terminals for supplying plural ground voltages with different voltage levels; and plural circuits using an output node commonly therebetween, and for inputting or outputting data to or from a memory cell, wherein each of the plural circuits is different from the other in drive voltage and includes: a MOS transistor of a first conductive type provided between a power supply node and the output node; and a MOS transistor of a second conductive type provided between the output node and a ground node, the MOS transistor of a first conductive type receiving a power supply voltage with the highest voltage level among the plural power supply voltages as a substrate voltage thereof from said power supply terminal and the MOS transistor of a second conductive type receiving a ground voltage with the lowest voltage level among the plural ground voltages as a substrate voltage thereof from said ground terminal.
Preferably, the power supply voltage with the highest voltage level coincides with a voltage supplied to a power supply node of a circuit whose drive voltage is the highest among the plural circuits, and the ground voltage with the lowest voltage level coincides with a voltage supplied to a ground node of a circuit whose drive voltage is the highest among the plural circuit.
Preferably, the semiconductor memory device further includes: a first switch circuit selecting a power supply voltage with the highest voltage level among the plural power supply voltages to give the selected power supply voltage to the MOS transistor of a first conductive type; and a second switch selecting a ground voltage with the lowest voltage level among the plural ground voltages to give the selected ground voltage to the MOS transistor of a second conductive type.
Preferably, the semiconductor memory device includes: a first comparison circuit comparing voltage levels of the plural power supply voltages therebetween to output a result of the comparison; a second comparison circuit comparing voltage levels of the plural ground voltages therebetween to output a result of the comparison; a first switch selecting a power supply voltage with the highest voltage level based on the result of the comparison from the first comparison circuit to give the selected power supply voltage to the MOS transistor of a first conductive type; and a second switch selecting a ground voltage with the lowest voltage level based on the result of the comparison from the second comparison circuit to give the selected ground voltage to the MOS transistor of a second conductive type.
Preferably, the semiconductor memory circuit further includes: a power supply voltage supply circuit selecting a power supply voltage with the highest voltage level based on voltage levels of the plural power supply voltages to give the selected power supply voltage to the MOS transistor of a first conductive type; and a ground voltage supply circuit selecting a ground voltage with the lowest voltage level based on voltage levels of the plural ground voltages to give the selected ground voltage to the MOS transistor of a second conductive type.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.